The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) circuit.
An output buffer constituted by a CMOS is currently used frequently. As shown by FIG. 3, a basic one is constituted by connecting to each other drains of a P-channel MOS (Metal Oxide Semiconductor) transistor and an N-channel MOS transistor, providing an output terminal at a connection point of these and connecting to each other gates thereof Accordingly, there causes a timing where the P-channel MOS transistor and the N-channel MOS transistor are simultaneously made ON and a feedthrough current is flown between power source terminals VDD and VSS. There has been provided an output buffer disclosed, for example, in Japanese Examined Patent Publication No. JP-B-7-107978 to restrain such a feedthrough current. According to the output buffer, as shown by FIG. 4, drains of a P-channel MOS transistor 20 and an N-channel MOS transistor 40 are connected to each other, an output terminal is provided at a connection point thereof and outputs from inverters 130 and 140 are supplied to gates thereof. Further, an output from an inverter for inputting 120 is outputted to inverters 122 and 124 and the inverters 122 and 124 supply outputs respectively to a transmission gate E constituted by transistors 126 and 128 and a transmission gate F constituted by transistors 136 and 138. The two transmission gates E and F respectively receive the output from the inverter 120 at the gates of the transistors 128 and 136 on one side and receive outputs from inverters 132 and 142 further delaying outputs from the inverters 122 and 124 at the gates of the transistors 126 and 138 on the other side. Thereby in respect of outputs from the transmission gates E and F, rise of the former is made earlier than rise of the latter and fall of the latter is made earlier than fall of the former. Thereby, the transistors 20 and 40 which are respectively made ON and OFF by the inverters 130 and 140 respectively receiving the outputs from the transmission gates E and F, are not made ON simultaneously whereby a feedthrough current is restrained.
However, the circuit of FIG. 4 becomes complicated since the circuit uses 7 of the inverters and 2 of the transmission gates other than 2 of the MOS transistors for outputting whereby the circuit scale is magnified.